Latch optimization in circuits generated from high-level descriptions - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 1996

Latch optimization in circuits generated from high-level descriptions

(1) , (2) , (2)
1
2

Résumé

In a gate-level description of a finite state machine (FSM), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples.

Dates et versions

hal-00618122 , version 1 (31-08-2011)

Identifiants

Citer

Ellen M. Sentovich, Horia Toma, Gérard Berry. Latch optimization in circuits generated from high-level descriptions. Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, Nov 1996, San Jose, CA, United States. pp.428-435 - ISBN: 0-8186-7597-7, ⟨10.1109/ICCAD.1996.569833⟩. ⟨hal-00618122⟩
121 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook Twitter LinkedIn More