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Communication dans un congrès
Latch optimization in circuits generated from high-level descriptions
Abstract : In a gate-level description of a finite state machine (FSM), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples.
https://hal-mines-paristech.archives-ouvertes.fr/hal-00618122
Contributeur : Magalie Prudon <>
Soumis le : mercredi 31 août 2011 - 17:06:50
Dernière modification le : jeudi 24 septembre 2020 - 17:22:33
Contributeur : Magalie Prudon <>
Soumis le : mercredi 31 août 2011 - 17:06:50
Dernière modification le : jeudi 24 septembre 2020 - 17:22:33