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Static Compilation Analysis for Host-Accelerator Communication Optimization

Abstract : We present an automatic, static program transformation that schedules and generates e cient memory transfers between a computer host and its hardware accelerator, addressing a well-known performance bottleneck. Our automatic approach uses two simple heuristics: to perform transfers to the accelerator as early as possible and to delay transfers back from the accelerator as late as possible. We implemented this transformation as a middle-end compilation pass in the pips/Par4All compiler. In the generated code, redundant communications due to data reuse between kernel executions are avoided. Instructions that initiate transfers are scheduled e ectively at compile-time. We present experimental results obtained with the Polybench 2.0, some Rodinia benchmarks, and with a real numerical simulation. We obtain an average speedup of 4 to 5 when compared to a naïve parallelization using a modern gpu with Par4All, hmpp, and pgi, and 3.5 when compared to an OpenMP version using a 12-core multiprocessor.
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Submitted on : Friday, October 19, 2012 - 11:52:01 AM
Last modification on : Wednesday, November 17, 2021 - 12:31:43 PM
Long-term archiving on: : Sunday, January 20, 2013 - 3:38:38 AM


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  • HAL Id : hal-00743496, version 1


Mehdi Amini, Fabien Coelho, François Irigoin, Ronan Keryell. Static Compilation Analysis for Host-Accelerator Communication Optimization. LCPC'2011 : The 24th International Workshop on Languages and Compilers for Parallel Computing, Sep 2011, Fort Collins, Colorado, United States. pp. 237-251. ⟨hal-00743496⟩



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