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Stress-induced lift-off method for kerf-loss-free wafering of ultra-thin (∼50 μm) crystalline Si wafers

Abstract : We present a new wafering method for the production of ultra-thin crystalline silicon. This new lift-off process, named SLIM-cut (for Stress-induced LIft-off Method), requires only the use of a screen-printer and a belt furnace; no ion-implanted, porous layer or additional thickening by epitaxy is needed to obtain high quality wafers in the thickness range of 50 μm without kerf loss. We deposit on a thick substrate a layer with mismatched coefficient of thermal expansion with respect to the substrate (for instance a metal layer). Upon cooling, the differential contraction induces a large stress field, which is released by the initiation and the propagation of a crack parallel to the surface. The concept has already been demonstrated successfully on both single and multi-crystalline silicon. Very clean self-standing crystalline films with an area of 25 cm2 have been obtained from a high quality wafer. Some Si layers were further processed into solar cells. The first unoptimized solar cell device with a very simple process (no back-surface field, no intentional texturing, heterojunction emitter) showed an energy conversion efficiency of 10.0% (1 cm2). This represents a silicon consumption already as low as 3.1 g/Wp (taking into account a polishing loss of 50 μm), and proves the conservation of the material quality during the process. The potential of the method is estimated by the development of a custom-made numerical model. The model uses a 2D finite element method and is able to propagate a crack in a multi-layered structure. The model proposes a concentric re-meshing in the region of the crack tip at every increment and a crack initiation and propagation based on maximum stress criteria
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Submitted on : Monday, July 22, 2013 - 9:28:20 AM
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Frédéric Dross, Aurélien Milhe, Jo Robbelein, Ivan Gordon, Pierre-Olivier Bouchard, et al.. Stress-induced lift-off method for kerf-loss-free wafering of ultra-thin (∼50 μm) crystalline Si wafers. 33rd IEEE Photovoltaic Specialists Conference, PVSC 2008, May 2008, San Diego, United States. pp.Article number: 4922741 - ISBN 9781424416417, ⟨10.1109/PVSC.2008.4922741⟩. ⟨hal-00846861⟩



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