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Rapport

Automatic Code Generation for SIMD Hardware Accelerators

Abstract : SIMD hardware accelerators o er an alternative to manycores when energy consumption and performance are critical. For scienti c computing, GPGPUs are used in many computers of the top-500. But embedded processors also use accelerators. However such heterogeneous platforms trade ease of developments for performance: The application code and the data must be split between the host and the accelerator, synchronizations and communications between host and accelerator must be added, and accelerator hardware constraints must be taken into account by the programmer. To ease application development, we present an algorithm to automatically externalize the execution of a parallel loop using a synchronous master/slave protocol. The source-to-source transformation process is incrementally consistent and the transformed code can be executed at any step of the transformation algorithm, which make application and compiler debugging easier and possible without the target hardware. This article details the source-to-source parallel loop externalization algorithm and the new elementary program transformations which are used. Unlike previous work based on annotations or polyhedral model, it relies on interprocedural array region analysis, which embraces more situations than the polyhedral model while still not relying on user input. It has been implemented in the PIPS framework and its results are given at each transformation step for an image processing example.
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https://hal-mines-paristech.archives-ouvertes.fr/hal-00881211
Contributeur : Claire Medrala <>
Soumis le : mardi 10 décembre 2013 - 16:14:01
Dernière modification le : mercredi 14 octobre 2020 - 03:52:19
Archivage à long terme le : : vendredi 14 mars 2014 - 09:26:46

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A-425.pdf
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  • HAL Id : hal-00881211, version 1

Citation

Serge Guelton, François Irigoin, Ronan Keryell. Automatic Code Generation for SIMD Hardware Accelerators. 2010. ⟨hal-00881211⟩

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