S. Ickin, K. Wac, M. Fiedler, L. Janowski, J. Hong et al., Factors influencing quality of experience of commonly used mobile applications, IEEE Communications Magazine, vol.50, issue.4, pp.48-56, 2012.
DOI : 10.1109/MCOM.2012.6178833

A. Carroll and G. Heiser, An analysis of power consumption in a smartphone, Proceedings of the USENIX conference on USENIX, 2010.

D. C. Snowdon, S. Ruocco, and G. Heiser, Power management and dynamic voltage scaling: Myths and facts, 2005 WS Power Aware Real-time Comput, 2005.

B. Gold and C. M. Rader, Digital Signal Processing, 1969.
DOI : 10.1002/9781118142882.ch6

N. H. Weste and K. Eshraghian, Principles of CMOS VLSI design: a systems perspective, 1985.

W. Liu, X. Jin, K. Kao, and C. Hu, BSIM 4.1.0 MOSFET model-user's manual, EECS Dept., Univ. of California, vol.48, 2000.

A. Agarwal, S. Mukhopadhyay, C. Kim, A. Raychowdhury, and K. Roy, Leakage power analysis and reduction: models, estimation and tools Computers and Digital Techniques, IEEE Proceedings, vol.152, issue.3, pp.353-368, 2005.

Y. You, C. Lee, and J. K. Lee, Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors, Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing, ser. LCPC'02, pp.45-60, 2005.
DOI : 10.1007/11596110_4

S. Mukhopadhyay, A. Raychowdhury, and K. Roy, Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling, Proceedings of the 40th conference on Design automation , DAC '03, pp.169-174, 2003.
DOI : 10.1145/775832.775877

H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif, Full chip leakage estimation considering power supply and temperature variations, Proceedings of the 2003 international symposium on Low power electronics and design , ISLPED '03, pp.78-83, 2003.
DOI : 10.1145/871506.871529

W. Liao, L. He, and K. M. Lepak, Temperature and supply Voltage aware performance and power modeling at microarchitecture level, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.7, pp.1042-1053, 2006.
DOI : 10.1109/TCAD.2005.850860

A. Ferre and J. Figueras, Characterization of leakage power in CMOS technologies, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196), pp.185-188, 1998.
DOI : 10.1109/ICECS.1998.814859

K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy et al., Temperature-aware microarchitecture, ACM Transactions on Architecture and Code Optimization, vol.1, issue.1, pp.94-125, 2004.
DOI : 10.1145/980152.980157

X. Fan, C. S. Ellis, and A. R. Lebeck, The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling, Proceedings of the Third international conference on Power -Aware Computer Systems, pp.164-179, 2004.
DOI : 10.1109/92.920816

B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, Theoretical and practical limits of dynamic voltage scaling, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.868-873, 2004.
DOI : 10.1145/996566.996798

B. Calhoun, A. Wang, N. Verma, and A. Chandrakasan, Sub-threshold design, Proceedings of the 2006 international symposium on Low power electronics and design , ISLPED '06, pp.366-368, 2006.
DOI : 10.1145/1165573.1165661

K. D. Vogeleer, G. Memmi, P. Jouvelot, and F. Coelho, The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices, TELE- COM ParisTech, 2013.
DOI : 10.1007/978-3-642-55224-3_74
URL : https://hal.archives-ouvertes.fr/hal-00919414