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Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors

Karel de Vogeleer 1, 2 Gérard Memmi 1 Pierre Jouvelot 3, 2 Fabien Coelho 2, 3
1 INFRES - Département Informatique et Réseaux
2 CRI - Centre de Recherche en Informatique
3 MINES ParisTech - École nationale supérieure des mines de Paris
Keywords : Computational modeling Voltage control Program processors Heating Leakage currents Temperature measurement Temperature distribution
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Conference papers
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https://hal-mines-paristech.archives-ouvertes.fr/hal-01111647
Contributor : Claire Medrala <>
Submitted on : Friday, January 30, 2015 - 4:52:08 PM
Last modification on : Friday, October 16, 2020 - 11:33:42 AM

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Karel de Vogeleer, Gérard Memmi, Pierre Jouvelot, Fabien Coelho. Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Jul 2014, Samos, Greece. pp 172-180, ⟨10.1109/SAMOS.2014.6893209⟩. ⟨hal-01111647⟩

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