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Compiling Image Processing Applications for Many-Core Accelerators

Pierre Guillou


Today, new many-core architectures strive to provide GPU-level performance with low energy consumption for embedded systems. The MPPA many-core chip, designed by the French company Kalray, is such an architecture, offering 256 compute cores while consuming on average 10W. These 256 cores are distributed into 16 clusters of 16 cores each, with a 2 MB shared memory per cluster. The chip also comprises 4 I/O clusters for allowing access to the outside world through common interfaces such as PCI-express, Ethernet or DDR. For easing the programming effort of porting one’s application onto the chip, several programming models can be used. In particular, Kalray proposes a dataflow programming language called Sigma-C. A dedicated compiler automatically generates communication code and maps tasks on available cores. Sigma-C applications are represented by directed graphs whose edges are streams of data and whose nodes, called agents, consume data on their input and produce data on their output. Using a source-to-source compiler, we generate Sigma-C code for the MPPA chip from image processing applications written in a high-level DSL. Our contribution include: * a small library of basic image processing operators written in Sigma-C, such as: – pixel-to-pixel arithmetic operators; – reductions on a whole image; – specific stencil operators consisting of a reduction over a pixel neighborhood and called morphological operators; * a Sigma-C dataflow graph code generator based on our library and implemented in a source-to-source compiler; * a run-time system to transfer images between a host system and the many-core chip and to manage dataflow graphs.
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Dates et versions

hal-01254412 , version 1 (12-01-2016)


  • HAL Id : hal-01254412 , version 1


Pierre Guillou. Compiling Image Processing Applications for Many-Core Accelerators . ACACES Summer School : Eleventh International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Jul 2015, Fiuggi, Italy. . ⟨hal-01254412⟩
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