Obstacle avoidance and navigation in the real world by a seeing robot rover, In tech., report CMU-RI-TR-80-03, 1980. ,
Zhang Zuxun,Parallel Algorithm of Harris Corner Detection Based on Multi-GPU, pp.876-881, 2012. ,
Accelerating Harris Algorithm with GPU for Corner Detection, 2013 Seventh International Conference on Image and Graphics ,
DOI : 10.1109/ICIG.2013.36
Patrice Rondao Alface,Low Complexity Corner Detector Using CUDA for Multimedia Applications, The Third International Conferences on Advances in Multimedia,IARIA, pp.978-979, 2011. ,
Low-complexity pruning for accelerating corner detection, 2012 IEEE International Symposium on Circuits and Systems, pp.1684-1687, 2012. ,
DOI : 10.1109/ISCAS.2012.6271582
Tamim Asfour2 ,Benjamin Oech- slein3, Christoph Erhardt3, Jens Schedel3, Daniel Lohmann3, and Wolfgang Schroder- Preikschat,Resource-Aware Harris Corner Detection based on Adaptive Pruning ,German Research Foundation (DFG) as part of the Transregional Collaborative Research Centre, Invasive Computing ,
A Novel Harris Mullti-scale Corner Detection Algorithm, Journal of Electronics Information Technology, vol.29, issue.7, pp.1735-1738, 2007. ,
ADaptive Harris Corner Detection Algorithm, Computer Engineering, vol.34, issue.10, pp.212-215, 2008. ,
A Fast and Accurate Corner Detector Based on Harris Algorithm, 2009 Third International Symposium on Intelligent Information Technology Application, pp.49-51, 2009. ,
DOI : 10.1109/IITA.2009.311
Tamim Asfour, Self-Adaptive Harris Corner Detector on Heterogeneous Many-Core Processor , German Research Foundation (DFG) as part of the Transregional Collaborative Research Centre, Invasive Computing ,
Shoal: smart allocation and replication of memory for parallel programs, USENIX Annual Technical Conference, 2015. ,
Automatically Optimizing Stencil Computationson Many-core NUMA Architectures,International Workshop on Languages and Compilers for Parallel Computing Rochester, 2016. ,
DOI : 10.1007/978-3-319-52709-3_12
Embracing diversity in the Barrelfish manycore operating system ,MMCS'08, 2008. ,
Traffic Management:A Holistic Approach to Memory Placement on NUMA Systems, ASPLOS'13, 2013. ,
URL : https://hal.archives-ouvertes.fr/hal-00945758
Thread and memory placement on NUMA systems: asymmetry matters, Proceedings of the 2015 USENIX Conference on Usenix Annual Technical Conference (USENIX ATC '15). USENIX Association, pp.277-289 ,
MemProf:A memory Profiler for NUMA Multicore Systems, USENIX ATC, p.2012 ,
URL : https://hal.archives-ouvertes.fr/hal-00945731
Adaptive Contention-Aware Thread Placement for Parallel Runtime Systems, 2015. ,
High Level Transforms for SIMD and Low-Level Computer Vision Algorithms Symposium on Principles and Practice of Parallel Programming, 2014. ,
NUMA-aware algorithms: the case of data shuffling http ,
High Level Transforms for SIMD and Low-level Computer Vision Algorithms, Workshop on Programming Models for SIMD/Vector Processing, pp.49-56, 2014. ,
DOI : 10.1145/2568058.2568067
Obstacle avoidance and navigation in the real world by a seeing robot rover, 1980. ,
Object tracking, ACM Computing Surveys, vol.38, issue.4, 2006. ,
DOI : 10.1145/1177352.1177355
Survey of appearance-based methods for object recognition, 2008. ,
Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE, LCTES'07, 2007. ,
SMO: An Integrated Approach to Intra-array and Inter-array Storage Optimization, ACM Symposium on Principles of Programming Languages, 2016. ,
DOI : 10.1145/2914770.2837636
URL : https://hal.archives-ouvertes.fr/hal-01425888
Improving Data Locality by Array Contraction, IEEE Transactions on Computers, vol.53, issue.9, 2004. ,
Automatic Collapsing of Non-Rectangular Loops, 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2017. ,
DOI : 10.1109/IPDPS.2017.34
URL : https://hal.archives-ouvertes.fr/hal-01581081
An Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems, IEEE Transactions on Computers, vol.36, issue.5, pp.603-614, 1987. ,
Parallelization schemes for memory optimization on the cell processor, Proceedings of the 2007 workshop on MEmory performance DEaling with Applications, systems and architecture, MEDEA '07, 2011. ,
DOI : 10.1145/1327171.1327172
URL : https://hal.archives-ouvertes.fr/hal-00753708
Accelerator-Based implementation of the Harris Algorithm, 5th International Conference on Image Processing, 2012. ,
DOI : 10.1007/978-3-642-31254-0_55
URL : https://hal.archives-ouvertes.fr/hal-00753803
Highly Parallel Implementation of Harris Corner Detector on CSX SIMD Architecture, th Workshop on Highly Parallel Processing on a Chip (HPPC), 2010. ,
DOI : 10.1007/978-3-642-10331-5_75
Pipelining Harris corner detection with a tiny FPGA for a mobile robot, 2013 IEEE International Conference on Robotics and Biomimetics (ROBIO), 2013. ,
DOI : 10.1109/ROBIO.2013.6739792
Performance evaluation of corner detectors using consistency and accuracy measures, Computer Vision and Image Understanding, vol.102, issue.1, pp.81-94, 2006. ,
DOI : 10.1016/j.cviu.2005.11.001
High Performance Computing as a Combination of Machines and Methods and Programming, 2013. ,
URL : https://hal.archives-ouvertes.fr/tel-00832930
ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems, 2008. ,
MAi: Memory Affinity interface, 2008. ,
URL : https://hal.archives-ouvertes.fr/inria-00344189